개인정보처리방침

개인정보처리방침

이 개인정보 처리방침은 000(전자거래 사업자)가 운영하는 사이버 몰(이하 ‘회사’ 라 한다)에서 제공하는 온라인 관련 서비스(이하 “서비스”라 한다)를 이용함에 있어 사이버몰과 이용자의 권리·의무 및 책임사항을 규정함을 목적으로 합니다.

회사는 개인정보 보호법 제30조에 따라 정보주체(고객)의 개인정보를 보호하고 이와 관련한 고충을 신속하고 원활하게 처리할 수 있도록 하기 위하여 다음과 같이 개인정보 처리지침을 수립․공개합니다.

1. 개인정보의 처리목적 회사는 다음의 목적을 위하여 개인정보를 처리하고 있으며, 다음의 목적 이외의 용도로는 이용하지 않습니다.
– 고객 가입의사 확인, 고객에 대한 서비스 제공에 따른 본인 식별․인증, 회원자격 유지․관리, 물품 또는 서비스 공급에 따른 금액 결제, 물품 또는 서비스의 공급․배송 등

2. 개인정보의 처리 및 보유기간 ① 회사는 정보주체로부터 개인정보를 수집할 때 동의받은 개인정보 보유․이용기간 또는 법령에 따른 개인정보 보유․이용기간 내에서 개인정보를 처리․보유합니다.
② 구체적인 개인정보 처리 및 보유 기간은 다음과 같습니다.
– 고객 가입 및 관리 : 서비스 이용계약 또는 회원가입 해지시까지, 다만 채권․채무관계 잔존시에는 해당 채권․채무관계 정산시까지
– 전자상거래에서의 계약․청약철회, 대금결제, 재화 등 공급기록 : 5년

3. 개인정보의 제3자 제공 회사는 정보주체의 별도 동의, 법률의 특별한 규정 등 개인정보 보호법 제17조에 해당하는 경우 외에는 개인정보를 제3자에게 제공하지 않습니다.

4. 회사는 위탁계약 체결시 개인정보 보호법 제25조에 따라 위탁업무 수행목적 외 개인정보 처리금지, 재위탁 제한, 수탁자에 대한 관리․감독, 책임에 관한 사항을 문서에 명시하고, 수탁자가 개인정보를 안전하게 처리하는지를 감독하고 있습니다.

5. 정보주체의 권리․의무 및 행사방법 정보주체는 회사에 대해 언제든지 다음 각 호의 개인정보 보호 관련 권리를 행사할 수 있습니다.
1. 개인정보 열람요구
2. 개인정보에 오류 등이 있을 경우 정정 요구
3. 삭제요구
4. 처리정지 요구

6. 처리하는 개인정보 항목 회사는 다음의 개인정보 항목을 처리하고 있습니다.
– 성명, 생년월일, 주소, 전화번호, 휴대전화번호, 성별, 이메일주소, 신용카드번호, 은행계좌번호 등 결제정보

7. 개인정보의 파기 ① 회사는 개인정보 보유기간의 경과, 처리목적 달성 등 개인정보가 불필요하게 되었을 때에는 지체없이 해당 개인정보를 파기합니다.
② 회사는 다음의 방법으로 개인정보를 파기합니다.
– 전자적 파일 : 파일 삭제 및 디스크 등 저장매체 포맷
– 수기(手記) 문서 : 분쇄하거나 소각

8. 개인정보의 안전성 확보조치 회사는 개인정보의 안전성 확보를 위해 다음과 같은 조치를 취하고 있습니다.
– 관리적 조치 : 내부관리계획 수립․시행, 직원․종업원 등에 대한 정기적 교육
– 기술적 조치 : 개인정보처리시스템(또는 개인정보가 저장된 컴퓨터)의 비밀번호 설정 등 접근권한 관리, 백신소프트웨어 등 보안프로그램 설치, 개인정보가 저장된 파일의 암호화
– 물리적 조치 : 개인정보가 저장․보관된 장소의 시건, 출입통제 등

9. 개인정보 보호책임자 회사는 개인정보 처리에 관한 업무를 총괄해서 책임지고, 개인정보 처리와 관련한 정보주체의 불만처리 및 피해구제를 처리하기 위하여 아래와 같이 개인정보 보호책임자를 지정하고 있습니다.

개인정보 보호책임자

연락처: 000@naver.com

10. 개인정보 처리방침 변경 이 개인정보 처리방침은 2021. 1. 30.부터 적용됩니다.

Cutting-edge Hyper-Scale AI Acceleration
Eco-Friendly ASICs Transforming the Cloud

info@soteria-sys.com

Cutting-edge Hyper-Scale AI Acceleration
Eco-Friendly ASICs Transforming the Cloud

info@soteria-sys.com

8th Floor, JLK Tower, Yeoksam-dong 678-29, Gangnam-gu, Seoul, South Korea
1290 Reamwoo Ave., Sunnyvale, CA 94089, USA

© 2023 SOTERIA INC. All rights reserved.

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Immersion Cooling is a highly efficient cooling solution that involves submerging servers in a non-conductive fluid.

Soteria’s Dependable Power Protection Circuit and Bad Core Management technology, along with firmware matching, are optimized for the maintenance of our client’s eco-friendly Data Center Immersion Liquid Cooling. This cooling method allows for direct contact between components and coolant, providing exceptional heat dissipation. Immersion cooling offers a myriad of benefits including improved cooling efficiency, reduced thermal stress, performance enhancement, extended equipment lifespan, and reduced physical installation space. Furthermore, immersion cooling eliminates the need for air cooling, allows for high-density placement, and reduces noise pollution in computing environments. This stunning, top-notch technology is the epitome of our commitment to innovative solutions and environmental responsibility.
  • Quiet operation
  • Lower CAPEX and OPEX (per kW)
  • Better TCO (per kW)
  • About 10x more heat rejection capacity
  • Less space required
  • More energy efficiency and sustainability

Logical/physical co-design

a. Grouping of tiling and hardening/basic processing elements (PEs) by application workload

b. Algorithm and gate-level optimization of critical operators ex) 4NM FinFET optimization Self-Shut-Off Pulsed Latches

 

c. PPAC(Power, Performance, Area, Cost) PE core enhancement and full chip layout for optimization

Optimized for customer operating environment

a. Dependable Performance Harvesting Technology – Patent Pending; Bad Core Management
b. Heat Dissipation Full Custom Layout

- 0.3V Library Re-Characterization and Near Threshold Computation

- Dependable Low Voltage IO Design supporting Fine-grained multi-power domain

- Undershoot / Overshoot Protection Circuit

- Revolutionizing Heat Transfer Design: Experience optimal thermal dissipation through our cutting-edge Hybrid P&R Layout technology, directly integrated into the ASIC for superior microchannel and heat sink performance. We guarantee the shortest heat dissipation path from the cells at the base to the RDL at the top, maximizing surface area contact with the cooling liquid for unparalleled thermal management.

- Experience Performance Beyond Limits: With the superior cooling efficiency of our immersion cooling systems, we empower higher operational frequencies without the risk of thermal throttling, pushing the boundaries of peak performance

- Soteria’s Advance Physical Implementation

Physical Implementation Engineer

Streamlined Logical-Physical Design Fusion:

Through meticulous tiling and hardening, we adapt to application workloads, ensuring optimal grouping of Primary Processing Elements (PE) for maximum efficiency and performance.

Enhancement of Vital Operators (Addressors, Multipliers, and more):

We achieve excellence through algorithmic and gate-level enhancements, such as advanced Dynamic, Domino Design, and asynchronous operation, to sharpen performance and deliver unprecedented results.

PE Core Strengthening and Comprehensive Chip Layout:

We strive for PPAC (Power, Performance, Area, Cost) optimization, reinforcing our Primary Processing Element (PE) cores and executing a full chip layout for maximum efficiency and cost-effectiveness.

Reliable Performance Harvesting Technology:

We focus on the management of Bad Cores and defective parts (ASIC Fault) to secure dependable performance. Our advanced technology effectively handles faults in ASICs, ensuring enhanced performance and stability.

Standard Cell based Full custom layout

  • Competitive TAT for post-layout timing analysis and timing closure
  • Ensure correct timing analysis at all design specific mode and corner combinations
  • In-house flow that makes full custom layout DB apply like Auto PnR DB
  • Configure physical hierarchy
  • Schematic vs physical cell binding
  • Update components and nets
  • Extract DEF and LEF2SPEF RC extraction

Signal & Power Integrity Engineer

Responsibilities and Opportunities

– Chip-level & Package-level SI/PI simulations.

– Collaborate with external SI/PI service providers

Key Qualifications

– Master’s degree or higher in EE

– Deep understanding of the theory of signal transmission and electromagnetic.

– Ability to work effectively in a production environment and deliver working solutions.

– Familiarity with IBIS AMI specification, model generation and simulation in commercial EDA tools such as Hspice and ADS.

Ideal Qualifications

– Experienced in designing HPC ASIC Accelerator Chip.

Physical Implementation Engineer

Responsibilities and Opportunities

– Implement the physical design (RTL2GDS, CDL2GDS) to achieve the best PPA.

– Support DSPs and/or contractors to do their best within the target TAT.

– Suggest architectural changes to improve the final QoR.

Key Qualifications

– Bachelor’s degree in Electrical Engineering or equivalent practical experience.

– 3 years of experience with EDA tool workflows in a semiconductor environment.

– Experience in scripting (e.g., Python, Tcl, Skill) for workflow automation and data visualization.

Ideal Qualifications

– Synthesis, STA, Simulation.

– Floorplan/Power planning, P&R, PV.

– CTS.

– V-XL/MXL P&R.

– Calibre LVS/DRC, StarRC.

– EM, PERC.

Global Marketing

Responsibilities and Opportunities

– Close external technology exchange with Samsung and DSP.

– Establishment of strategies and plans related to domestic semiconductor support projects.

– Visualize and document technology development reports.

– Understand market trends and proceed with internal reflection process.

– Responding to overseas customers and managing customers.

– Marketing Performance Indicators Management.

– General Import and export business.

Key Qualifications

– Semiconductor product marketing experience.

Ideal Qualifications

– Samsung (Foundry, SLSI, Memory) Marketing Experience.

SoC Engineer

Responsibilities and Opportunities

– Co-work closely with cross-functional teams for integrating SoC.

– Co-work and communicate with DSP for SoC implementation.

– Co-work for performing silicon bring-up and debug.

Key Qualifications

– Experience on multiple core CPU sub-system.

– Experience with various peripherals such as UART, SPI, I2C, I2S, GPIO and so on.

Ideal Qualifications

– Proficiency with industry-standard EDA tools relating to SoC integration.

Front-End Design (AI ASIC design)

Position Overview

We are looking for a talented engineer with a minimum of 8 years of experience to join our Front-End Design team. This role focuses on AI Accelerator ASIC and NPU architecture design and optimization. The ideal candidate will have a strong background in RTL design, verification, and a comprehensive understanding of AI/Machine Learning algorithms.

Key Responsibilities

– Design and implementation of front-end architectures, including DC and STA.

– RTL design and verification using Verilog and VHDL.

– FPGA prototype development for AI accelerators.

– Performance analysis and power efficiency optimization.

– Integrated design and optimization of software and hardware components.

– Chip architecture design and logic verification.

– Collaboration with cross-functional teams to ensure seamless integration of designs.

– In-depth analysis and enhancement of data center and cloud computing environments.

Skills and Qualifications

Educational Background

– Bachelor’s or Master’s degree in Electrical and Electronic Engineering, Semiconductor Engineering, or a related field.

Technical Expertise

– Proficient in RTL design and verification (Verilog, VHDL).

– Skilled in FPGA prototype development.

– Expertise in performance analysis and power efficiency optimization.

– Strong understanding of AI/Machine Learning algorithms.

– Knowledge of data center and cloud computing environments.

Tools Proficiency

– Verdi, VCS, DC, PrimeTime (STA, PTPX), Formality, Spyglass.

Preferred Qualifications

– Experience in integrated software and hardware design.

– Strong problem-solving skills and ability to work in a collaborative environment.

Location

– Soteria lab in Pangyo, Republic of Korea

Front-End Design Engineer (Near Data Process design)

Position Overview

We are looking for a talented engineer with a minimum of 8 years of experience to join our Front-End Design team. The focus of this role is on Near Data Processing architecture design and optimization. The ideal candidate should have expertise in RTL design, verification, and experience with memory interface and PCIe protocol architecture

Key Responsibilities

– Design and implementation of front-end architectures, including DC and STA.

– RTL design and verification using Verilog and VHDL.

– FPGA prototype development for Near Data Processing systems.

– Design and optimization of memory interface architecture.

– Architecture design and implementation of PCIe protocol.

– Chip architecture development and logic verification.

– Collaboration with cross-functional teams to ensure effective integration of designs.

Skills and Qualifications

Educational Background

– Bachelor’s or Master’s degree in Electrical and Electronic Engineering, Semiconductor Engineering, or a related field.

Technical Expertise

– Proficient in RTL design and verification (Verilog, VHDL).

– Skilled in FPGA prototype development.

– Expertise in memory interface architecture design and optimization.

– Strong understanding of PCIe protocol architecture design and implementation.

Tools Proficiency

– Verdi, VCS, DC, PrimeTime (STA, PTPX), Formality, Spyglass.

Preferred Qualifications

– Experience in integrated software and hardware design.

– Strong analytical skills and ability to work collaboratively within a team.

Location

– Soteria lab in Pangyo, Republic of Korea

Submit Applications to HR@SOTERIA-SYS.COM